In various semiconductor processing schemes, high aspect ratio features are etched into stacks of material. Example applications include, but are not limited to, memory applications such as fabrication of DRAM and 3D NAND devices. Often, the stacks include dielectric material, and may include alternating layers of materials such as oxide and nitride or oxide and polysilicon. After the high aspect ratio features are etched (e.g., to form recessed cylinders, trenches, etc.), a selective etch process occurs to etch back one of the materials in the stack. In some cases, a liner material may be deposited after this selective etch. Material (e.g., metal, polysilicon, or dielectric in many cases) is then deposited along the sidewalls of the feature, including within the areas that were selectively etched back. This material must then be removed in order to electrically isolate the material deposited in each region that was previously selectively etched back. This process scheme is further discussed below with reference to FIGS. 1A-1E.